Design of physically unclonable functions in cmos and emerging technologies for hardware security applications

Abstract

The advent of the IoT scenario heavily pushed the demand of preserving the information down to the chip level due to the increasing demand of interconnected devices. Novel algorithms and hardware architectures are developed every year with the aim of making these systems more and more secure. However, IoT devices operate with constrained area, energy and budget thus making the hardware implementation of these architectures not always feasible. Moreover, these algorithms require truly random key for guarantying a certain security degree. Typically, these secret keys are generated off chip and stored in a non-volatile manner. Unfortunately, this approach requires additional costs and suffers from reverse engineering attacks. Physically unclonable functions (PUFs) are emerging cryptographic primitives which exploit random phenomena, such as random process variations in CMOS manufacturing processes, for generating a unique, repeatable, random, and secure keys in a volatile manner, like a digital fingerprint. PUFs represent a secure and low-cost solution for implementing lightweight cryptographic algorithms. Ideally PUF data should be unique and repeatable even under noisy or different environmental conditions. Unfortunately, guarantying a proper stability is still challenging, especially under PVT variations, thus requiring stability enhancement techniques which overtake the PUF itself in terms of required area and energy. Nowadays, different PUF solutions have been proposed with the aim of achieving ever more stable responses while keeping the area overhead low. This thesis presents a novel class of static monostable PUFs based on a voltage divider between two nominally identical sub-circuits. The fully static behavior along with the use of nominally identical sub-circuits ensure that the correct output is always delivered even when on-chip noise occasionally flips the bit, and that randomness is always guaranteed regardless of the PVT conditions. Measurement results in 180-nm CMOS technology demonstrates the effectiveness of the proposed solution with a native instability (BER) of only 0.61% (0.13%) along with a low sensitivity to both temperature and voltage variations. However, these results were achieved at the cost of more area-hungry design (i.e., 7,222𝐹 ) compared to other relevant works. The proposed solution was also implemented with emerging paper based MoS2 nFETs by exploiting a LUT-based Verilog-A model, calibrated with experimental 𝐼 vs 𝑉 at different 𝑉 curves, whose variability was extracted from different 𝐼 vs 𝑉 curves of 27 devices from the same manufacturing lot. Simulations results demonstrate that these devices can potentially used as building block for next generation electronics targeting hardware security applications. Finally, this thesis also provides an application scenario, in which the proposed PUF solution is employed as TRNG module for implementing a smart tag targeting anti-counterfeiting applications.