An Analog/Mixed-Signal SoC-Package Co-Design Methodology for Early Stage Signal Integrity Assessment Exploiting the Potential of Machine Learning Models
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Settino, Francesco
Crupi, Felice
Palestri, Pierpaolo
Brandtner, Thomas
Koffler, Harald
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Università della Calabria. Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica. Dottorato di ricerca in Information and Communication Technologies (ICT); The development of new generation System-on-Chip (SoC) is mainly driven by
the demand of an ever increasing number of functionalities at reduced cost and
time-to-market. This is enabled by re-using specialized functional blocks, generally
referred as intellectual property (IP) blocks. However, each block (analog, digital,
analog mixed-signal) is typically designed and optimized independently either inhouse
or by a third-party vendor. This leads to an increased design complexity,
making the integration of the analog mixed-signal (AMS) blocks very challenging.
As the switching behavior (di/dt and dv/dt) of the chip signals increases due to
higher clock frequency, the package and board interconnects start to contribute
significantly to the overall system-level performance. Signal integrity is a main
issue in package designs due to the parasitic effects of capacitive/inductive coupling
between potential aggressor and victim signals. In general, fast switching signals
can induce unwanted disturbances into sensitive signals due to crosstalk effects even
via off-chip interconnects, which may degrade significantly the overall system-level
performance.
A SoC for automotive applications typically requires several high accuracy
analog-to-digital converters (ADCs), which are key blocks to sense and process the
external inputs in order to quickly react at system-level (especially for safety requirements).
However, those ADCs need to be integrated in a complex environment that
comprises many different IP blocks (e.g. power converter or high-speed interfaces) at
high switching frequency that can act as potential aggressors. Hence, next generation
of SoC will face a significantly higher number of aggressor-victim couples. On the
other hand, more accurate mixed-signal circuitries such as voltage monitoring will
be required especially for advanced driver assistance systems (ADAS) application
due to safety requirements. Reliable and accurate prediction of the system-level behavior by chip-packageboard
co-design is essential to achieve “right first time” solutions. A machine learning
approach can save significant time considering the main challenges in performing
system-level simulations, mainly related to circuit complexity and convergence issue
due to the integration of the package model (typically S-parameter data). This
research work focuses on the development of a methodology exploiting machine
learning algorithm to enable optimized SoC-Package co-design right from the early
stage of the development cycle. The main target is to detect potential specification
violation issues at system-level that may occur due to signal integrity challenge at
package-level, providing guidelines for package design, and a quick feedback for the
chip design development towards the optimization of the overall chip-package-board
system, optimizing development cycles and time-to-market for competitive products.Soggetto
CHIP-PACKAGE CO-DESIGN; COCO-SIMULATION METHODOLOGY; SIGNAL INTEGRITY; EM SIMULATION; MACHINE LEARNING
Relazione
ING-INF/01;