New methodologies and instrumentations for power semiconductor devices testing

Abstract

Nowadays electronic applications involve a high density of power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) which represent the major percentage of energy flow to be controlled. Moreover, new technologies, such as Silicon Carbide (SiC), have been well involved in the existing power applications. Therefore, the reliability of power devices is highly demanded. Since decades, a widely used accelerated test to evaluate the reliability of MOSFETs is the so-called High Temperature Reverse Bias (HTRB). In this stress test, the Devices Under Test (DUTs) are reverse polarized at a certain percentage of the rated breakdown voltage and maintained in this condition at high temperature for a determined long time. A typical HTRB test also incorporates Electrical Characterization Tests (ECTs) of DUTs before and after each stress period, seeking for failed devices. However, time elapsed between ECTs are long and degradation and failure information of DUTs might not be registered. In this context, an advanced methodology for HTRB test is proposed. The latter consists of applying more stress cycles of short duration together with more frequent ECTs at a relatively high temperature that can be directly compared to that of normal operation in power applications (i. e. 125 °C). With this methodology, more detailed information about degradation trends in electrical parameters, time of failures and stopping of stress test on degrading devices before full breakdown can be performed. The latter can be very useful in R&D stages, where the post-failure analysis of well-degraded devices, but not broken, is important. An automatized instrumentation, aimed to apply this methodology, has been implemented. The latter utilizes individual Thermal Control Modules (TCMs) to control the test temperature per single DUT. The temperature control is performed through an opposite mini-heater and firmware running on an 8-bit microcontroller. TCMs can be set remotely to apply test temperatures in the range [30-200 °C]. In addition, Switch Matrix Modules (SSMs) are implemented to configure the electrical connections required for HTRB or ECT tests remotely. A PC application controls all the modules through a Master Communication Module (MCM) also implemented. A commercial Source and Measure Unit (SMU) is used for the electrical stress. Full customization of HTRB and ECTs test parameters can be performed to optimize the stress and degradation data acquisition. Combining the advanced methodology and instrumentation above mentioned, more stressful conditions can be applied to shorten the overall test time without losing the electrical degradation trends of failing devices. In fact, features of the implemented instrumentation allow for controlling unbeneficial thermal runaway process on the single device, isolating thermal and electric of degraded devices, acquiring frequently electrical parameters data, performing ECTs at a relatively high temperature between shorter stress cycles, managing real-time control of HTRB test. These features are useful to get reliability data in a shorter time than a typical application of HTRB tests while preserving DUTs for post-failure analysis. The advanced methodology and automatized instrumentation have been applied to Si and SiC power MOSFETs with interesting results, demonstrating to be suitable for both shorter and more accelerated HTRB tests to acquire critical information necessary for the study of degradation processes and reliability in power devices. Moreover, results have demonstrated that degradation trends are not affected when more frequent ECTs at slightly different temperature are performed in the DUTs. In addition, accurate test results have shown that drawbacks of typical HTRB implementation have been solved through the advanced methodology and instrumentation reported. Complementing the work presented, Low-Frequency Noise Measurements (LFNMs) were also applied as valuable tool to investigate the degradation process in power MOSFETs after stressing them through HTRB test. A correlation between the results from advanced HTRB test and LFNM in power MOSFETs demonstrates that the electrical degradation is represented by a noise spectrum different to that for intrinsic 1/f noise.